High resolution flat panel for radiation imaging

ABSTRACT

A high resolution flat panel for radiation imaging includes an array of pixels arranged in rows and columns. Gate lines interconnect the pixels of the rows while source lines interconnect the pixels of the columns. Gate driver circuits provide gate pulses to the gate lines in succession in response to input from a control circuit to select the pixels on a row-by-row basis. The source lines lead to charge amplifiers for sensing the signal charges stored by the pixels when the pixels are selected. At least one pair of adjacent pixels in each row of the array shares a source line. Gating of the pairs of pixels in the rows that share a source line is controlled by control logic to ensure that signal charges stored by only one of those pixels is applied to a shared source line at a time. This allows the number of charge amplifiers in the flat panel to be reduced while maintaining high resolution.

TECHNICAL FIELD

The preset invention relates to imaging systems and in particular to ahigh resolution flat panel for radiation imaging and to a compensationcircuit for an amplified flat panel for radiation imaging.

BACKGROUND ART

Flat panels for radiation imaging have been extensively studied for overten years, and are well known in the art. Examples of flat panels forradiation imaging can be found in the following patents:

U.S. Pat. Nos. 5,132,541, 5,184,018, 5,396,072 and 5,315,101 assigned toPhilips;

U.S. Pat. Nos. 4,785,186 and 5,017,989 assigned to Xerox;

U.S. Pat. Nos. 4,382,187, 4,799,094, 4,810,881, and 4,945,243 assignedto Thomson-CSF;

U.S. Pat. Nos. 5,182,624, 5,254,480, 5,368,882, 5,420,454, 5,436,458 and5,444,756 assigned to 3M;

U.S. Pat. Nos. 5,079,426 and 5,262,649 assigned to Michigan University;

U.S. Pat. Nos. 5,340,988, 5,399,884, 5,480,810, 5,480,812 and 5,187,369assigned to General Electric; and

U.S. Pat. No. 5,315,102 assigned to Fuji Xerox.

One type of flat panel radiation imaging system includes a thickamorphous selenium (a-Se) film on an array of pixels such as thatdescribed in the article entitled “Flat Panel Detector for DigitalRadiology Using Active Matrix readout of Amorphous Selenium,” by W. Zhaoet al., Medical Imaging 96, SPIE Conference, SPIE 2708, February 1996.In this flat panel radiation imaging system, the pixels are arranged inrows and columns with each pixel including a TFT switch. Gate linesinterconnect the TFT switches in each row of the array while source ordata lines interconnect the TFT switches in each column of the array.The thick amorphous selenium film is deposited directly on top of theTFT switch array and a top electrode overlies the amorphous seleniumfilm.

When x-rays are incident on the amorphous selenium film and the topelectrode is biased with a high voltage, electron-hole pairs areseparated by the electric field across the thickness of the amorphousselenium film. The holes, which are driven by the electric field, movetoward the pixel electrodes (i.e. the drain electrodes of the TFTswitches) and accumulate in a storage capacitor in each pixel. Thisresults in a charge being held by the pixel electrodes which can be usedto develop an x-ray image.

The charges held by the pixel electrodes are read on a row-by-row basisby supplying gating pulses to each gate line in succession. When agating pulse is supplied to a gate line, the TFT switches of the pixelsin the row associated with that gate line turn on, allowing the signalcharges stored in the storage capacitor of those pixels to flow to thesource lines. Ideally, the TFT switches of the array should becontrolled only by the potential voltage on the gate electrode. However,stray electric fields from the amorphous selenium film and the topelectrode, which can be up to 10V/m, can have significant effects on thechannel conductance of the TFT switches unless special shieldingtechniques are used. One such shielding technique is to provide adual-gate structure in the TFT switches. In these TFT switches, one gateis disposed below the semiconductor channel layer and the other gate ispositioned above the semiconductor channel layer. The two gates areelectrically connected together. An example of a dual-gate TFT switch isdisclosed in “IEEE Transactions on Electronic Devices-28, No.6,pp.740-743, June 1981” by F. C. Luo et al.

Also, in medical x-ray imaging systems, signal levels are generally muchlower than visible light imaging systems, in order to minimize theexposure of patients to x-rays. Therefore, in order to obtain highresolution, a high signal to noise ratio is extremely important. Inorder to improve the signal to noise ratio in x-ray imaging systems,amplified imaging pixels for flat panels have been considered such asthose described in the “IEEE Journal of Solid-State Circuits, Vol. SC-4,No.6, pp. 333-342, December 1969” by S.G. Chamberlain and in the“Proceedings of IEDM'93, pp 575-578, December 1993” by H. Kawashima etal.

In order to reduce the switch noise caused by parasitic capacitancedistributed along the source lines and maximize the signal to noiseratio, a charge amplifier is provided for each column of TFT switches inthe pixel array. The charge amplifiers sense the charges on the sourcelines when a row of pixels is gated and provide output voltage signalsproportional to the charges and hence, proportional to the exposure ofthe pixels to radiation. Unfortunately, by providing a charge amplifierfor each source line, two problems result. Firstly, in large formatradiation imaging systems which include in excess of one thousand (1000)source lines, the cost associated with the charge amplifiers issignificant. Secondly, in high resolution radiation imaging systems thathave a small pixel pitch, it is difficult to wire-bond the chargeamplifiers to each source line. Accordingly, there is a need for animproved high resolution flat panel for radiation imaging.

It is therefore an object of the present invention to provide a novelhigh resolution flat panel for radiation imaging and a compensationcircuit for an amplified flat panel which obviates or mitigates at leastone of the above-mentioned problems.

DISCLOSURE OF THE INVENTION

According to one aspect of the present invention there is provided aflat panel for radiation imaging comprising:

a radiation transducer to be exposed to incident radiation;

an array of pixels on one side of said radiation transducer, each ofsaid pixels including a storage capacitor to store signal chargeproportional to the exposure of said radiation transducer to radiationin the vicinity of said pixels;

a plurality of gate lines interconnecting the rows of pixels in saidarray, said gate lines receiving gate pulses to allow said pixels to beselected on a row-by-row basis;

a plurality of source lines interconnecting the columns of pixels insaid array to allow the signal charges held by the storage capacitors ofsaid selected pixels to be sensed, at least one pair of adjacent pixelsin each row sharing a source line; and

control means to control selection of the pixels sharing a source lineso that the signal charge stored by the storage capacitor of only onepixel of each pair can be sensed by way of a shared source line at atime when said row of pixels is selected.

Preferably, the flat panel has multiple pairs of adjacent pixels in eachrow that share source lines. In one embodiment, during the first halftime period of a gate pulse, the control means biases one pixel of thepairs of pixels sharing a source line to allow the signal charges heldby those one pixels to be selected in response to the gate pulse, andduring the remaining half time period of the gate pulse, the controlmeans biases the other pixel of the pairs of pixels sharing a sourceline to allow the signal charges held by those other pixels to beselected in response to the gate pulse.

It is also preferred that the flat panel includes refresh means torefresh the storage capacitors of the pixels after the signal chargesheld thereby have been sensed. In one embodiment, each row of pixels isrefreshed as the next row of pixels is being selected. In a differentembodiment, the pixels of the flat panel are refreshed after all of therows of pixels have been selected.

According to yet another aspect of the present invention there isprovided a compensation circuit for use in a high resolution amplifiedflat panel for radiation imaging comprising:

an amplifier having an input terminal to receive amplified signal chargeoutput on a source line by a selected pixel of said flat panel inresponse to a gate pulse, said amplified signal charge having a dc bias;and

switch means to connect said input terminal to a potential voltagesource when said amplified charge is received, said potential voltagesource having a magnitude substantially the same as said dc bias butopposite in polarity to offset said dc bias.

The present invention provides advantages in that the need for a chargeamplifier associated with each column of TFT switches in the array isobviated. This is achieved by allowing adjacent pixels in the rows ofthe array to share a source line and therefore a charge amplifier. Thepixels sharing a source line are gated at different times to ensure thatthe signal charge stored by only one of those pixels is applied to ashared source line at a time to avoid mixing of signal charges andtherefore maintain high resolution.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described more fullywith reference to the accompanying drawings in which:

FIG. 1 is a schematic of a high resolution amplified flat panel forradiation imaging in accordance with the present invention;

FIG. 2 is a top plan view of a pixel forming part of the high resolutionamplified flat panel of FIG. 1;

FIG. 3 is a cross-sectional view of the pixel of FIG. 2 taken along line3—3;

FIG. 4 is a schematic of an alternative embodiment of a high resolutionamplified flat panel for radiation imaging in accordance with thepresent invention;

FIG. 5 is a schematic of yet another alternative embodiment of a highresolution amplified flat panel for radiation imaging in accordance withthe present invention;

FIG. 6 is a schematic of a high resolution flat panel for radiationimaging in accordance with the present invention;

FIG. 7 is a top plan view of a pixel forming part of the high resolutionflat panel of FIG. 6;

FIG. 8 is a cross-sectional view of FIG. 7 taken along line 8—8;

FIG. 9 is a schematic of an alternative embodiment of a high resolutionflat panel for radiation imaging in accordance with the presentinvention;

FIG. 10 is a schematic of a compensation circuit for use in the highresolution amplified flat panels of FIGS. 1 to 5; and

FIG. 11 is a timing diagram of the driving pulses generated duringoperation of the high resolution amplified flat panel of FIG. 1.

BEST MODES FOR CARRYING OUT THE INVENTION

Referring now to FIG. 1, a high resolution amplified flat panel forradiation imaging is shown and is generally indicated to by referencenumeral 20. The flat panel 20 includes an array of pixels 22 arranged inrows and columns. In this particular example, the array is shown toinclude two rows and four columns. It should however be understood thatthis is for illustrative purposes only and that the array will typicallyinclude a significant number of pixels. Gate lines 24 interconnect thepixels 22 in the rows of the array while source lines 26 interconnectthe pixels 22 in the columns of the array. The gate lines 24 lead to agate driver circuit 28. The gate driver circuit 28 provides gate pulsesto the gate lines in succession in response to input from a controlcircuit 30 to allow signal charge held by the pixels 22 in the array tobe sensed on a row-by-row basis so that a radiation image of a subjector object can be developed.

The source lines 26 lead to charge or current amplifiers 32 (hereinafterreferred to collectively as charge amplifiers) for sensing the signalcharge held by the pixels 22. The charge amplifiers 32 provide output toan analog multiplexer 34. The analog multiplexer 34 provides imageoutput which can be digitized to create a digitized radiation image ofthe subject or object in response to input from the control circuit 30.As can be seen, the second and third pixels 22 in each row share asource line 26 thereby allowing the number of charge amplifiers requiredto sense signal charge held by the pixels to be reduced as compared withconventional flat panels.

Control lines 40 also interconnect the pixels 22 in the columns of thearray. The odd-numbered control lines are connected to a first buss 42while the even-numbered control lines are connected to a second buss 44.Buss 42 leads to a switch 46 which is actuable to connect the buss 42either to ground 48 or to a positive potential voltage source 50. Buss44 leads to a switch 52 which is actuable to connect the buss either toground 48 or to the potential voltage source 50. The switches 46 and 52are controlled so that only one of the busses 42 or 44 is able to beconnected to the potential voltage source 50 at a time.

Each pixel 22 in the array includes three thin film transistor (TFT)switches 60, 62 and 64 as well as a storage capacitor 66. TFT switch 62,is of a dual-gate structure and has a top gate electrode and a bottomgate electrode, the two of which are electrically connected. TFT switch62 acts as an amplifier to amplify the signal charge held by the storagecapacitor 66 and output a modulated drain current proportional to theheld signal charge. The storage capacitor 66 is connected to the gateelectrodes of TFT switch 62. Thus, signal charge stored by the storagecapacitor 66 changes the gate potential of TFT switch 62 and in turnmodulates its drain current. TFT switch 60, which can be of a dual-gateor a single-gate structure (as shown in FIG. 2), acts as a switch toconnect the TFT switch 62 to the source line 26 to allow the modulateddrain current of TFT switch 62 to flow to the charge amplifier 32. TheTFT switch 64 acts as a reset switch to clear the signal charge held bystorage capacitor 66 after the modulated drain current of TFT switch 62has been sensed by the charge amplifier 32 and thereby refresh the pixel22. The configuration of the pixels 22 will now be described further.

The array of pixels 22, the gate lines 24, the source lines 26 and thecontrol lines 40 are formed on a common glass substrate 70. FIGS. 2 and3 better illustrate one of the pixels 22. As can be seen, TFT switch 60has a gate electrode 72 constituted by a portion of a gate line 24. Asemiconductor material channel layer 74 formed of Cadmium Selenide(CdSe) is deposited over the gate electrode 72 and is spaced from it bya gate insulating layer 76. The source electrode 78 of the TFT switch 60contacts the channel layer 74 by way of a via 80 formed in a passivationlayer 82 overlying the channel layer 74 and the gate insulating layer76. The source electrode 78 is constituted by a portion of a source line26. The drain electrode 84 of the TFT switch 60 contacts the channellayer 74 by way of a via 86 formed in the passivation layer 82. Thedrain electrode 84 of TFT switch 60 is electrically connected to thesource electrode 88 of the TFT switch 62.

The source electrode 88 of TFT switch 62 contacts the channel layer 90of the TFT switch by way of a via 92 formed in the passivation layer 82.The drain electrode 94 of TFT switch 62 also contacts the channel layer90 by way of a via 96 formed in the passivation layer 82 and isconstituted by a portion of a control line 40. A bottom gate electrode98 runs beneath the channel layer 90 and is spaced from it by the gateinsulating layer 76. The bottom gate electrode 98 is connected to a topgate electrode 100 by way of a pair of vias 102 formed in the gateinsulating and passivation layers 76 and 82 respectively. The top gateelectrode 100 overlies a common buss 104 connected to ground. The topgate electrode 100 and common buss 104 define the plates of the storagecapacitor 66.

The top gate electrode 100 is also connected to the source electrode 106of TFT switch 64. The source electrode 106 contacts the channel layer108 of TFT switch 64 by way of a via 110 formed in the passivation layer82. The drain electrode 112 of the TFT switch 64 contacts the channellayer 108 by way of a via 114 formed in the passivation layer 82 and isconstituted by a portion of a control line 40. The gate electrode 116 ofTFT switch 64 is constituted by a portion of another gate line 24.

Deposited on the array of pixels 22 is a radiation transducer 54. Theradiation transducer 54 includes a layer of radiation sensitive material56 and a top electrode 58 overlying the radiation sensitive material 56.It is preferred that the radiation sensitive material is in the form ofa thick chalcogenide film including selenium, tellurium and otherdopants such arsenic and fluor-complex. The top electrode 58 is biasedby a voltage which is high enough to drive signal charges in the bulk ofthe layer of radiation sensitive material 56 towards the top gateelectrodes 100 commonly referred to as pixel electrodes.

In operation, the top electrode 58 is biased to a high voltage and theflat panel 20 is exposed to incident radiation which has passed throughthe subject of object to be imaged. As the incident radiation interactswith the layer of radiation sensitive material 56, electron-hole pairsare generated and then separated by the electric field created acrossthe thickness of the layer of radiation sensitive material 56. The holesare driven by the electric field towards and are accumulated by the topgate electrodes 100 of TFT switches 62. This results in signal chargesbeing held by the storage capacitors 66 of the pixels 22 which areproportional to the amount of incident radiation on the pixels 22.

After the flat panel 20 has been exposed to incident radiation, thesignal charges accumulated by the top gate electrodes 100 and held bythe storage capacitors can be sensed on a row-by-row basis to allow aradiation image of the subject or object to be developed. The operationof the flat panel 20 to allow the signal charges stored by the storagecapacitors 66 to be sensed will now be described with particularreference to FIGS. 1 and 11.

Initially, the switches 46 and 52 are connected to ground 48 so that nopotential voltage exists on the control lines 40. A gate pulse VG1 isthen applied to the first gate line 24 which causes all of the TFTswitches 60 in the first row of pixels 22 to turn on. When the TFTswitches 60 in the first row of pixels turn on, the drain currents ofTFT switches 62 are ready to flow onto the source lines 26 through theTFT switches 60. However, the drain currents of the TFT switches 62 aredominated by both the potential on their gate electrodes and the sourceand drain electrode voltages. Since the source lines 26 are groundedthrough the charge amplifiers 32 and since no potential voltage existson the control lines 40, the drain currents of TFT switches 62 are notoutput to the source lines 26 through the TFT switches 60.

Shortly after the gate pulse VG1 is applied to the first gate line 24,the switch 46 is actuated to connect buss 42 to the potential voltagesource 50 for a duration ts which is significantly smaller than theduration of the gate pulse VG1. At this time, the control lines 40connected to the buss 42 supply a potential voltage to the drainelectrodes of the TFT switches 62 and 64 connected to them. Once thedrain electrodes of the TFT switches 62 are biased by the potentialvoltage source 50, each TFT switch 62 connected to buss 42 by way ofcontrol line 40 supplies drain current, which has been modulated by thesignal charge held by the storage capacitor 66, to the associated sourceline 26 through the TFT switch 60. The modulated drain currents suppliedto the source lines 26 are in turn sensed by the charge amplifiers 32.

After duration ts, the switch 46 is actuated to connect buss 42 toground to return the TFT switches 62 that were conducting to anoff-condition. Shortly thereafter and while the gate pulse VG1 is stillbeing applied to the first gate line 24, the switch 52 is actuated toconnect the buss 44 to the potential voltage source 50 for a durationts. At this time, the control lines 40 connected to the buss 44 supply apotential voltage to the drain electrodes of the TFT switches 62 and 64connected to them. Once the drain electrodes of the TFT switches 62 arebiased by the potential voltage source 50, each TFT switch 62 connectedto buss 44 by way of control line 40 supplies drain current, which hasbeen modulated by the signal charge held by the storage capacitor 66, tothe associated source line 26 through the TFT switch 60. The modulateddrain currents supplied to the source lines 26 are in turn sensed by thecharge amplifiers 32.

After the duration ts, the switch 52 is actuated to connect the buss 44to ground to return the TFT switches 62 that were conducting to anoff-condition. The gate pulse VG1 is continued on the first gate line 24for a duration tr and is then stopped. Once the gate pulse VG1 hasended, a gate pulse VG2 is applied to the second gate line 24 and theabove sequence of events is performed to allow the modulated draincurrents of the TFT switches 62 in the pixels 22 of the second row to besensed. Once the drain currents for all of the pixels 22 in the secondrow have been sensed and during duration tr, the control lines 40 areconnected to ground 48 by way of busses 42 and 44 and switches 46 and52. Thus, no current flows to the source lines 26. However, the gatepulse VG2 is applied to the gate electrodes of the TFT switches 64 inthe first row. The gate pulse VG2 in turn causes the TFT switches 64 inthe first row to turn on. When the TFT switches 64 turn on, the top gateelectrodes 100 and storage capacitors 66 of the pixels 22 in the firstrow are connected to the control lines 40. Since the control lines 40are grounded, the storage capacitors 66 and top gate electrodes 100 alsobecome grounded to remove signal charges held by the storage capacitorand thereby refreshing all of the pixels 22 in the first row.

The above steps are of course repeated until each row of pixels 22 inthe flat panel 20 has received a gate pulse to allow the signal chargesheld by the storage capacitors to be sensed and each row of pixels hasbeen refreshed.

As one of skill in the art will appreciate, the flat panel 20 allows thesignal charge held by the storage capacitors 66 of the pixels 22 in thearray to be sensed on a row-by-row basis while reducing the number ofcharge amplifiers as compared with prior art designs. This is achievedby allowing pairs of pixels in each row to share source lines andallowing the signal charge held by only one pixel of each pair to besensed on the shared source line at a time.

Referring now to FIG. 4, another embodiment of a high resolutionamplified flat panel 20 b is shown. In this embodiment, like referencenumerals will be used to indicate like components of the firstembodiment with a “b” added for clarity. In this embodiment, the storagecapacitors 66 b in each row of pixels 22 b are connected to a buss 111.The busses 111 are interconnected and lead to a switch 113 which isactuable to connect the busses either to ground 115 or to a potentialvoltage source 117. This particular configuration allows the potentialvoltage applied to the gate electrodes of TFT switches 62 b to becontrolled through storage capacitors 66 b by actuating the switch 113to change the potential on the busses.

The operation of the flat panel 20 b is very similar to that of theprevious embodiment except that the busses 111 are connected to thepotential voltage source 117 by way of switch 113 in order to modulatethe output drain current of TFT switches 62 b during sensing of thesignal charges held by the storage capacitors 66 b. If desired, thebusses 111 can also be connected to the potential voltage source 117 byway of switch 113 when the pixels in the rows are being refreshed.

Referring now to FIG. 5, yet another alternative embodiment of a highresolution amplified flat panel 20 c for radiation imaging is shown. Inthis embodiment, like reference numerals will be used to indicate likecomponents of the first embodiment with a “c” added for clarity. In thisembodiment, the odd-numbered gate lines 24 c lead to a gate drivercircuit 28 c on one side of the array of pixels 22 c while theeven-numbered gate lines 24 c lead to a gate driver circuit 28 c on theopposite side of the array of pixels 22 c. The buss 42 c receives acontrol bias from a control node 200 by way of an amplifier 202 whilethe second buss 44 c receives a control bias from the control node 200by way of a delay circuit 204 and a second amplifier 206. The delaycircuit 204 ensures that only one of the two busses 42 c and 44 c has alogic high control bias provided on it at a time and is synchronizedwith the gate pulse applied to each gate line 24 c. In this manner,during a gate pulse, buss 42 c receives a potential voltage for aduration ts during the first half of the gate pulse and following that,buss 44 c receives a potential voltage for a duration ts during theremaining half of the gate pulse. Refresh lines 208 also interconnectthe pixels 22 c in the rows of the array. The refresh lines 208 areinterconnected and lead to a switch 210 which is actuable to connect therefresh lines either to ground 212 or to a positive potential voltagesource 214.

As can be seen, unlike the previous embodiments the rows of pixels 22 cdo not share gate lines 24 c or refresh lines 208 with the previous orfollowing rows of pixels. Also, the rows of pixels 22 c are notrefreshed until all of the rows of pixels 22 c in the flat panel 20 chave been readout. During signal charge readout, the operation of theflat panel 20 c is very similar to that of the previous embodiments.Thus, signal charge stored by the storage capacitors 66 c in each row ofpixels are readout on a row-by-row basis. The pairs of pixels in eachrow that share a source line 26 c are controlled during readout so thatonly one pixel of each pair applies modulated drain current to thesource lines 26 c at a time. Once all of the rows of pixels have beenreadout, the switch 210 is actuated to connect the refresh lines 208 tothe potential voltage source 214. The bias applied to the refresh linesis applied to the gate electrodes of all of the TFT switches 64 ccausing the TFT switches 64 c to turn on. When the TFT switches turn on,the gate electrodes of TFT switches 62 c and the storage capacitors 66 care connected to the control lines 40 c. During this period, the controllines 40 c are grounded to remove signal charge held by the storagecapacitors 66 c and TFT switches 62 c and thereby refresh the pixels 22c.

Referring now to FIG. 10, a compensation circuit for use in a highresolution amplified flat panel for radiation imaging is shown and isindicated to generally by reference numeral 400. The compensationcircuit 400 can be used with any of the flat panels previously describedwith reference to FIGS. 1 to 5. As can be seen, the compensation circuit400 includes a transistor switch 402 associated with each of the sourcelines 426. The gate 404 of each transistor switch 402 is connected to acontrol bus 406. The source 408 of each transistor switch 402 isconnected to the associated source line 426. The drain 410 of eachtransistor switch 402 is connected to another bus 412 leading to anegative potential voltage source 414. The magnitude of the potentialvoltage source 44 is selected so that it is approximately equal to themagnitude of the modulated drain current applied to a source line by aselected pixel which is located in a dark region of a radiation image.

When the amplified flat panels are being gated and the signal chargesheld by the storage capacitors are being readout, the modulated draincurrents applied to the source lines 426 have a positive dc componentresulting from the TFT switches 62 which act as amplifiers. To offsetthis dc component, when the modulated drain currents are being sensed, acontrol signal is applied on control bus 406 to turn the transistorswitches 402 on. When the transistor switches 402 are turned on, thesource lines 426 are connected to the negative potential voltage source414 by way of transistor switches 402 and the bus 412 to compensate forand offset the dc bias.

Referring now to FIGS. 6 to 8, an embodiment of a high resolutionnon-amplified flat panel for radiation imaging is shown and is generallyindicated to by reference numeral 220. The flat panel 220 includes anarray of pixels 222 arranged in rows and columns. Gate lines 224interconnect the pixels 222 of the rows while source lines 226interconnect the pixels 222 of the columns. The odd-numbered gate lines224 lead to a gate driver circuit 228 on one side of the array of pixels222 while the even-numbered gate lines 224 lead to a gate driver circuit228 on the opposite side of the array of pixels 222. The gate drivercircuits 228 provide gate pulses to the gate lines 224 in succession inresponse to input from a control circuit 230 to allow signal charge heldby the pixels 222 in the array to be sensed on a row-by-row basis sothat a radiation image of a subject or object can be developed.

The source lines 226 lead to charge amplifiers 232 for sensing thesignal charge held by the pixels 222. The charge amplifiers provideoutput to an analog multiplexer 234. The analog multiplexer 234 providesimage output which can be digitized to create a digitized radiationimage in response to input from the control circuit 230. As can be seen,the first and second pixels and third and fourth pixels 222 in each rowshare a source line 226.

Control lines 240 also interconnect the pixels 222 in the even-numberedcolumns of the array of pixels. The control lines 240 are connected to abuss 242 which leads to a switch 246. The switch 246 is actuable eitherto connect the buss 242 to a high potential node 248, in this embodimentground, or to a low potential node 250, in this embodiment −15V.

In this embodiment, each pixel 222 includes two TFT switches 260 a and260 b. TFT switch 260 a can be a single-gate or a dual-gate structure.TFT switch 260 b is of a dual-gate structure. Thus, in the particularexample shown, the TTF switches 260 a in the odd-numbered columns of thearray are of a single-gate structure while the TFT switches 260 b in theeven-numbered columns of the array are of a dual-gate structure.

The array of pixels 222, the gate lines 224, the source lines 226 andthe control lines 240 are formed on a common glass substrate 270. FIGS.7 and 8 better illustrate two adjacent pixels 222 in a row of the arrayof pixels 222. As can be seen, TFT switch 260 a has a gate electrode 272constituted by a portion of a gate line 224. A semiconductor materialchannel layer 274 formed of Cadmium Selenide (CdSe) is deposited overthe gate electrode 272 and is spaced from it by a gate insulating layer276. The source electrode 278 of the TFT switch 260 a contacts thechannel layer 274 by way of a via 280 formed in a passivation layer 282overlying the channel layer 274 and the gate insulating layer 276. Thesource electrode 278 is constituted by a portion of a source line 226.The drain electrode 284 of the TFT switch 260 a contacts the channellayer 274 by way of a via 286 formed in the passivation layer 282. Thedrain electrode 284 of TFT switch 260 a overlies a common buss 304connected to ground. The drain electrode 284 and common buss 304 definethe plates of a storage capacitor 266.

The source electrode 288 of TFT switch 260 b contacts the drainelectrode 284 of TFT switch 260 a as well as a channel layer 290 by wayof a via 292 formed in the passivation layer 282. The drain electrode294 of TFT switch 260 b also contacts the channel layer 290 by way of avia 296 formed in the passivation layer 282. The drain electrode 294also overlies the common buss 304 to define the plates of anotherstorage capacitor 266. A bottom gate electrode 298 runs beneath thechannel layer 290 and is spaced from it by the gate insulating layer276. A top gate electrode 300 is deposited on the passivation layer 282between the source and drain electrodes 288 and 294 respectively andoverlies the channel layer 290. The top gate electrode 300 isconstituted by a portion of the control line 240.

Deposited on the array of pixels 222 is a radiation transducer 254. Theradiation transducer 254 includes a layer of radiation sensitivematerial 256 and a top electrode 258 overlying the radiation sensitivematerial 256. The top electrode 258 is biased by a voltage which is highenough to drive signal charges in the bulk of the layer of radiationsensitive material 256 towards the drain electrodes 284 and 294.

When the flat panel 220 has been exposed to incident radiation, thestorage capacitors 266 of each pixel 222 hold a signal charge which isproportional to the exposure of the flat panel to radiation in thevicinity of the pixels 222. When it is desired to sense the storedsignal charges, a gate pulse is applied on the first gate line 224.Prior to applying the gate pulse on the first gate line 224, the switch246 is conditioned to connect the buss 242 to the negative potentialvoltage source 250. The negative potential voltage is therefore appliedto the top gate electrodes 300 of the dual-gate TFT switches 260 b inthe first row preventing them from turning on in response to the gatepulse applied to the first gate line 224.

However, the gate pulse applied to the gate line 224 causes thesingle-gate TFT switches 260 a in the row to turn on thereby connectingthe drain electrodes 284 to the source lines 226 allowing the signalcharge held by the drain electrodes 284 to be discharged on the sourcelines 226 and sensed by the charge amplifiers 232. This readout processis continued on a row-by-row basis until half of the pixels 222 in eachrow (i.e. the pixels in the odd-numbered columns of the array) have beensensed.

Once all of the pixels 222 in the odd-numbered columns of the array havebeen sensed, the switch 246 is actuated to connect the buss 242 toground 248. Another gate pulse is then applied to the first gate line224 which causes all of the TFT switches 260 a and 260 b in the row toturn on. Thus, the storage capacitors 266 are connected to the sourcelines 226 through the TFT switches 260 a and 260 b allowing the signalcharges held by the storage capacitors 266 to be discharged on thesource lines 226 and sensed by the charge amplifiers 232. Gate pulsesare then applied to the remaining gate lines in succession to allow theremaining pixels 222 to be sensed.

Referring now to FIG. 9, an alternative embodiment of a high resolutionnon-amplified flat panel is shown and is generally indicated to byreference numeral 320. The flat panel 320 is very similar to that of theprevious embodiment. However, unlike the previous embodiment, thedual-gate TFT switches 360 b are connected directly to a. source line326. Therefore, when the signal charges held by the storage capacitors366 are to be sensed, the signal charges are discharged on to the sourcelines 326 only through the TFT switches 260 b.

As those of skill in the art will appreciate, the high resolution flatpanels allow radiation images to be developed while reducing the numberof charge amplifiers required. This is achieved by allowing pairs ofpixels in the same row of the pixel array to share source lines andcontrolling the gating of those pixels so that the signal charge held byonly one pixel of each pair is allowed to be sensed on a source line ata time. In the particular embodiments of FIGS. 1 to 5, the held signalcharges are amplified by the pixels before being discharged on thesource lines while in the embodiments of FIGS. 6 to 9, the held signalcharges are not amplified.

Although a number of embodiments of flat panels for radiation imaginghave been disclosed, those of skill in the art will appreciate thatvariations and modifications may be made without departing from thescope of the present invention as defined by the appended claims.

What is claimed is:
 1. A flat panel for radiation imaging comprising: aradiation transducer to be exposed to incident radiation; an array ofpixels on one side of said radiation transducer, each of said pixelsincluding a storage capacitor to store signal charge proportional to theexposure of said radiation transducer to radiation in the vicinity ofsaid pixels; a plurality of gate lines interconnecting the rows ofpixels in said array, said gate lines receiving gate pulses to allowsaid pixels to be selected on a row-by-row basis; a plurality of sourcelines interconnecting the columns of pixels in said array to allowsignal charges held by the storage capacitors of said selected pixels tobe sensed, at least one pair of adjacent pixels in each row sharing asource line; and control means to control selection of the pixelssharing a source line so that the signal charge stored by the storagecapacitor of only one pixel of each pair can be sensed by way of ashared source line at a time when said row of pixels is selected.
 2. Aflat panel as defined in claim 1 wherein multiple pairs of adjacentpixels in each row share source lines.
 3. A flat panel as defined inclaim 2 further including refresh means to refresh the storagecapacitors of said pixels after the signal charges held thereby havebeen sensed.
 4. A flat panel as defined in claim 3 wherein the pixels ofsaid pairs of adjacent pixels are positioned on opposite sides of saidshared source line.
 5. A flat panel as defined in claim 4 wherein saidcontrol means biases one pixel of each pair of pixels sharing sourcelines in a manner to allow said one pixel to be selected in response toa first portion of a gate pulse and then biases the other pixel of eachpair of pixels sharing said source lines in a manner to allow said otherpixel to be selected in response to the remaining portion of said gatepulse.
 6. A flat panel as defined in claim 5 wherein said control meansincludes control lines interconnecting columns of pixels in said arrayand a pair of busses, each of said busses being connectable to apositive potential voltage source or to ground by way of a switch, thecontrol lines interconnecting adjacent columns of pixels sharing asource line being connected to different busses, said switches beingcontrolled so that one of said busses biases said one pixels of saidpairs of pixels during said first portion of said gate pulse and so thatthe other of said busses biases said other pixels of said pairs ofpixels during said remaining portion of said gate pulse.
 7. A flat panelas defined in claim 5 wherein each of said pixels includes an amplifierto amplify signal charge held by said storage capacitors when beingsensed by way of said source lines.
 8. A flat panel as defined in claim7 further including a compensation circuit to offset dc bias applied tosaid amplified signal charges by said amplifiers.
 9. A flat panel asdefined in claim 3 wherein said refresh means refreshes said storagecapacitors of a previous row of pixels during selection of a followingrow of pixels.
 10. A flat panel as defined in claim 3 wherein saidrefresh means refreshes said storage capacitors of all of said pixelsafter all rows of said pixels have been selected.
 11. A flat panel asdefined in claim 2 wherein said control means biases one pixel of saidpairs of pixels sharing a source line in a manner to inhibit said onepixels from being selected during a first gate pulse and then biasessaid one pixels in a manner to allow said one pixels to be selected inresponse to a second gate pulse applied on the same gate line.
 12. Aflat panel as defined in claim 11 wherein said first gate pulses areapplied to each of said gate lines prior to applying said second gatepulses to said gate lines.
 13. A flat panel as defined in claim 12wherein said control means includes control lines interconnectingalternate columns of pixels in said array and a buss, said buss beingconnectable between a low potential voltage node and a high potentialvoltage node by way of a switch, said switch being controlled so thatsaid buss is connected to said low potential voltage node during saidfirst gate pulses to inhibit selection of said one pixels and so thatsaid buss is connected to said high potential voltage node during saidsecond gate pulses to permit selection of said one pixels.
 14. A flatpanel as defined in claim 13 wherein the pixels of said pairs ofadjacent pixels are positioned on opposite sides of said shared sourceline.
 15. A flat panel as defined in claim 13 wherein the pixels of saidpairs of adjacent pixels are positioned on the same side of said sharedsource line, one pixel of said pairs being connected directly to saidsource line and the other pixel of said pairs being connected to saidsource line through said one pixels.